//`timescale 1ns / 100 fs

//`include "e203_defines.v"

module led
	(
		input wire CLK_IN,	
        input wire RST_N,
		output wire LED0,        
		output wire LED1,        
		output wire LED2

	);

   
    reg [25:0] pre_cnt;
	    

	initial
	begin
		pre_cnt=26'b0;
	end		
	
    //PLL, produce sys_clk
    //    
    wire sys_clk;	
		
	PLL clkpll(		
		.refclk (CLK_IN),	
		.reset (~RST_N),	
		.clk0_out (coreclk),		
		.clk1_out (sys_clk)		
	);
	

	
endmodule
